In an EEPROM memory, the logic value of a logic datum, or bit, stored in a memory cell is represented by an off or on state of the memory cell and more precisely by the value of the threshold voltage of a floating gate transistor (also referred to as the state transistor). The on or off states of the memory cell may be modified at will in a write cycle generally comprising an erasing operation followed by a programming operation, where both of these operations are implemented using relatively high voltages.
FIG. 1 is a cross-sectional view of a conventional EEPROM memory cell 10 implemented as an integrated circuit and FIG. 2 shows a schematic circuit diagram of the conventional EEPROM memory cell 10. See, for example, FIGS. 1-2 of United States Patent Application Publication No. 2018/0033487 (incorporated by reference). A semiconductor substrate layer (bulk or semiconductor on insulator—SOI) 12 that is lightly doped with a first conductivity type dopant (for example, p-type) includes an active area 14 where the memory cell 10 is located. The active area 14 may, for example, be delimited by structure as needed for the memory application. The memory cell 10 includes an n-channel floating gate transistor 20 and an access transistor 22 (also referred to as the selection transistor). The source-drain paths of the floating gate transistor 20 and access transistor 22 are coupled in series between a source line (SL) 24 (connected to the source of transistor 20) and a bit line (BL) 26 (connected to the drain of transistor 22).
The floating gate transistor 20 includes a source region 32 in the active area 14 of the semiconductor substrate layer 12 that is heavily doped with a second conductivity type dopant (for example, n-type), a drain region 34 in the active area 14 of the semiconductor substrate layer 12 that is also heavily doped with the second conductivity type dopant, and an implant zone 48 (that is an extension of the drain region 34) in the active area 14 of the semiconductor substrate layer 12 that is also heavily doped with the second conductivity type dopant. A channel region 36 for the floating gate transistor 20 is located between the source region 32 and the implant zone 48. A gate structure for the floating gate transistor 20 is located over the channel region 36 and includes a floating gate electrode 42 and a control gate (CG0) electrode 44. The floating gate electrode 42 is separated from the channel region 36 and the implant zone 48 by a gate oxide layer 46 which includes a relatively thicker layer portion 46a, also referred to as the high voltage gate oxide, formed on the source side of the floating gate transistor 20, and a relatively thinner layer portion 46b, also referred to as the tunnel gate oxide, formed on the drain side of the floating gate transistor 20. The floating gate electrode 42 is insulated from the control gate (CG0) electrode 44 by an oxide-nitride-oxide (ONO) tri-layer. A tunnel injection zone 50 is located at the drain side of the floating gate transistor 20 corresponding to the location of the tunnel gate oxide layer portion 46b. The implant zone 48 underneath the tunnel gate oxide layer portion 46b is known in the art as a capacitor implant (“capa implant”) zone because its presence below the gate creates a capacitor structure. The capa implant zone 48 behaves like the channel of an “on” NMOS transistor where the channel is in strong inversion. The channel provided by the capa implant zone 48 under the gate is always present, unlike a conventional enhanced NMOS transistor which requires the gate voltage to exceed the MOS threshold voltage in order to form the N channel below the gate. The capa implant zone 48 is positioned in contact with, and functions as an extension of, the drain region 34 and is laterally dimensioned to distance the tunnel injection zone 50 from the drain-channel junction of the floating gate transistor 20. In this regard, it will be noted that the relatively thicker layer portion 46a of the gate oxide 46 is present over the capa implant zone 48 between the tunnel injection zone 50 and the edge of the capa implant zone 48 at the drain-channel junction. Relatively speaking, the dopant concentration level in the implant zone 48 can be greater than or less than the dopant concentration level in the drain region 34 (for example, having a dopant concentration in the range of 1×1017 to 1×1019 at/cm3), and the implant zone 48 may extend deeper (as shown) or shallower into the semiconductor substrate layer 12 than the depth of the drain region 34.
The access transistor 22 uses the drain region 34 as its source region, and further includes a drain region 38 in the semiconductor substrate layer 12 that is also heavily doped with the second conductivity type dopant. A channel region 40 for the access transistor 22 is located in the semiconductor substrate layer 12 between the regions 34 and 38. A gate structure for the access transistor 22 is located over the channel region 40 and includes a gate electrode 62 that is short-circuited to a word line (WL) 64 by connections (not shown in the figure) present along the length of the word line 64. The gate electrode 62 is insulated from the channel region 40 by a gate oxide layer 66. The gate oxide layer 66 may, for example, have a thickness which is equal to, or greater than, the thickness of the relatively thicker layer portion 46a. 
There are well known trade-offs between design selection of the tunnel gate oxide layer portion 46b thickness, the memory cell erase and program voltages and the memory cell erase and program threshold shifts.
Turning first to tunnel oxide thickness: at a given voltage across the tunnel layer a thinner thickness of the tunnel gate oxide layer portion 46b will provide for a higher electric field, and accordingly a higher Fowler-Nordheim current. As a result, the memory cell erase and program threshold shifts will be higher. However, satisfactory data retention in the memory cell requires the thickness of the tunnel gate oxide layer portion 46b to exceed some determinable minimum value. A thinner tunnel gate oxide layer portion 46b increases the likelihood of high trap-assisted tunneling and reduces reliability of data retention. In balancing these factors, memory cell designers have found that a thickness of 7-8 nm, for example, for the tunnel gate oxide layer portion 46b is satisfactory.
Turning next to memory cell erase and program voltages: higher voltages permit the use of a thicker tunnel gate oxide layer portion 46b and support better data retention. Additionally, higher voltages allow for lower coupling factors, more compact memory cells and improved cell endurance. However, the higher voltages are also seen by other transistors involved in accessing the memory cell (such as the access transistor 22, the control gate switching transistors, and bit line and word line decoding transistors). As memory cell area shrinks, it becomes difficult to make these other transistors compact while still being able to withstand the high voltage levels. So, acceptable voltage levels for memory cell erase and program should typically not exceed 13-15V.
With respect to the memory cell erase and program threshold shifts, this refers to the threshold differences of erased and programmed memory cells in comparison to the threshold of a so-called “virgin” cell which has no charge stored on the floating gate. These threshold shifts are converted by sense amplifiers to logic levels. A plurality of sense amplifiers are provided for a memory array, with these sense amplifiers operating to read a corresponding plurality of memory cells in parallel. A fast access time requires a significant threshold shift away from the virgin threshold so that the sense amplifiers can switch quickly. In an ideal case, the logical switching of the sense amplifier is centered at the virgin threshold. It is recognized, however, that it is quite difficult to ensure that two different sense amplifiers behave in the same way; for example, by having the same offset. The switching points of the plural sense amplifiers will not be the same, and will not be exactly centered in a way to ensure an optimal erasing condition. There is also a spread of the virgin thresholds across plural memory cells of the array, as well as a spread in erase and program threshold shifts across plural memory cells of the array. All taken into account, a safe threshold shift for the erased or programmed state is considered to equal or exceed +/−1V.
The threshold shift for the memory cell increases with larger applied voltages, thinner tunnel oxide thickness and longer duration pulses for erase and program operations. The maximum write time of the memory cell is equal to the sum of the duration of the erase pulse and the program pulse. A typical write time is on the order of 5 ms. The write time is typically a fixed value.
The operation to erase the memory cell 10 is as follows: a first voltage (for example, +13V) is applied to the control gate CG0 and a second voltage (for example, 0V) is applied to both the source line SL and the bit line BL. The floating gate electrode is coupled to the control gate (with a factor of about 0.7) to receive a third voltage (for example, +9V). The tunnel gate oxide layer portion 46b according sees a voltage of about +9V and the floating gate discharges through the tunnel oxide. At the end of the erase cycle, a negative charge of about 1V is present on the floating gate electrode.
The operation to program the memory cell 10 is as follows: the second voltage (for example, 0V) is applied to the control gate CG0. The first voltage (for example, +13V) is applied to the bit line BL. The word line WL voltage is set to +16V so that the source goes to bit line voltage of +13V due to body effect. Floating gate coupling to the source of the select transistor (with a factor of about 0.3) results in a voltage of +3.9V at the floating gate electrode. The tunnel gate oxide layer portion 46b according sees a voltage of about +9.1V (13V−3.9V) and the floating gate charges through the tunnel oxide. At the end of the program cycle, a positive charge of about 1V is present on the floating gate electrode.
It will be noted from the foregoing operational description that the applied voltage for memory cell erase and program is not fully seen by the tunnel gate oxide layer portion 46b. This is due to continuity of electric field at the tunnel gate oxide layer portion 46b/floating gate electrode and tunnel gate oxide layer portion 46b/implant zone 48 (capa implant). During erase operations there is a depletion at the floating gate electrode with a corresponding voltage drop. During program operations there is a depletion at the implant zone 48 (capa implant) with a corresponding voltage drop.
These voltage losses reduce the voltage seen across the tunnel gate oxide layer portion 46b window. So, for a given erase or program voltage level, the final ΔVt (erase or program) across the tunnel gate oxide layer portion 46b window is reduced by this voltage loss. The voltage loss is typically higher during program phases because the depletion of the implant zone 48 (capa implant) is larger than the depletion of the floating gate electrode during erase phases. In any event, this voltage loss must be compensated for with a corresponding increase of the erase or program voltage level. This increase in voltage level of the memory cell erase and program can be undesirable for the reasons noted above.
To maintain an acceptable voltage level for memory cell erase and program operation, it is accordingly desirable to minimize the voltage loss. One way to accomplish this goal would be to increase the dopant concentration level of the implant zone 48 (capa implant). There are a number of drawbacks to this solution. First, the increased dopant concentration produces a reduction in the avalanche voltage at the edge between the channel 36 and capa implant 48 for the floating gate transistor 20. As a result, it will become impossible achieve a rise in voltage at the implant zone 48 (capa implant) to +13V, because avalanche breakdown will occur at the junction at a voltage level lower than +13V. Second, the increase in dopant concentration level in the implant zone 48 (capa implant) can lead to an increase in lateral diffusion and shortening of the effective length of the channel for the floating gate transistor 20. The reduction in effective length may induce a decrease in transistor threshold voltage with a corresponding increased risk of instability and leakage of the floating gate transistor 20.
There is accordingly a need in the art for a better solution to achieve a minimization of the voltage loss so as to increase the voltage at the implant zone 48 (capa implant) without needing to also increase the erase or program operation voltage level.